This invention relates to the structure of a three-dimensional stacked LSI.
In a three-dimensional stacked LSI, silicon single-crystal layers wherein, devices such as transistors are formed of three-dimensionally stacked together with interlayer insulators therebetween, whereas, in conventional integrated circuits, devices are integrated in a plane. Because of its structure, a three-dimensional stacked LSI provides the following advantages in addition to improved integration density: first, the wiring length is far shorter than wiring length among plural planes since three-dimensional interlayer wiring is possible. As a result, signal propagation delay time is shortened and power dissipation is reduced. Second, it is suited for ultra-parallel processing since it allows a number of signals in the same plane to be simultaneously transferred between layers.
In preparing a three-dimensional stacked LSI, it is necessary to stack on already formed devices a silicon single-crystal layer through the intermediary of an interlayer insulator such as silicon dioxide and work it into the devices. Laser annealing and electron beam annealing have been developed as techniques for growing layer crystals. In both methods, silicon single crystals are obtained by locally melting poly-crystalline or amorphous silicon by means of a laser or an electron beam and recrystallizing the same. Thus, in the processes of forming the silicon single-crystal layer on top, forming the gate insulating film, activating the impurity doping, and so on, the wiring and devices are exposed to high temperatures. The low-melting-point metal (e.g. aluminium) wiring adopted in ordinary integrated circuits will easily react or melt at these process temperatures, thereby causing problems such as disconnection. In view of this, a heat-resistant wiring material which does not melt or easily react at these process temperatures must be employed in a three-dimensional stacked LSI. Tungsten, titanium, and molybdenum, or a silicide thereof, are known to be suitable as this heat-resistant wiring material. However, these metals exhibit an electrical resistance an order of magnitude higher than aluminum, which is used in ordinary integrated circuits. For instance, the electrical resistance of a 0.8 .mu.m thick aluminum sheet is 0.05 .OMEGA./.quadrature., whereas that of a 0.3 m thick tungsten sheet is about 0.5 .OMEGA./.quadrature.. The electrical resistance might be lowered by augmenting the film thickness. However, an excessive film thickness is undesirable from the viewpoint of stress and planarization.
Now, using a material with a high electrical resistance for wiring involves various problems including circuit malfunction due to voltage drop and operation speed reduction. In particular, a voltage drop in the power wiring constitutes a problem in the case of a three-dimensional stacked LSI performing a highly parallel circuit operation. For, in a parallel circuit, the number of devices which simultaneously operate increases in proportion to the degree of parallelism of the circuit, resulting in an increase in the dissipation current of the entire circuit, and in the case of a CMOS the circuit, an increase in the peak value of the dissipation current. In a three-dimensional stacked LSI which returns highly parallel processing, a voltage drop due to the power wiring resistance results in a reduction in operation speed, a reduced operation margin, malfunction of the logic gates, etc. If, in the case of a high-resistance wiring, a mask layout is adopted in which a wide power-wiring is used and in which priority is given to this wide powerwiring over other kinds of wiring with a view to eliminating the above problem, the power wiring will inevitably surround the devices, resulting in a large layout area and a lowered degree of flexibility in the layout of the inter-device signal wiring.